1. Technical Field
This invention generally relates to semiconductor devices, and more specifically relates to methods and structures to improve electrostatic discharge (ESD) and power-to-failure robustness in high current and high voltage environments.
2. Background Art
Modem semiconductor devices are highly susceptible to damage from electrical overstress (EOS), electrostatic discharge (ESD), as well as overvoltage and overcurrent conditions. EOS and ESD events can be caused by static charge from machines and people induced EOS events, ESD events, electromagnetic (EM) interference, EM field induction, and other processes.
Many commonly used integrated circuits contain elements, such as MOSFET transistors, resistors, capacitors and interconnects that can fail when a ESD event occurs. As a result, on-chip ESD protection circuitry, off-chip circuitry, and package solutions are used for EOS/ESD protection of integrated semiconductor devices.
One method of protecting devices from ESD damage is to provide ESD protection structures that drain ESD current before the voltage damages the device, without interfering with the normal operation of the device. To do this an ESD structure is connected to every input and output pin on a chip. With the ESD structure connected in parallel to every pin, ESD pulses can be safely drained away from the devices before damage is done to the device.
FIG. 27 is a cross sectional schematic view of a representative prior art ESD structure 800. The ESD structure 800 comprises a dual diode structure that can be used to provide ESD protection in a variety of applications. The dual-diode ESD structure 800 simplistically consists of a p-n diode connected between the pad node and the Vdd power supply and a second diode between the pad node and substrate ground.
The ESD structure 800 is fabricated in a p-type substrate 802. Not shown in the figure is a guard ring that defines the perimeter of the ESD structure 800. The guard ring preferably comprises a N+ region diffused into an N-well. The guard ring is typically connected to a positive bias Vdd and serves to collect electrons injected within the ESD structure before the electrons diffuse toward neighboring circuits and cause latch-up there. Inside the guard ring are a plurality of diffused regions comprising the dual diode ESD structure.
The ESD device 800 is also connected to bias Vdd at several diffusion regions. In particular, Vdd is connected to N++ diffusion 816 and N++ diffusion 812 inside N-well 808 and to N++ diffusion 820 inside N-well 804 . With Vdd connected to N-well 808, the N-well 808/p-substrate 802 junction is normally reversed biased, with no appreciable current flowing to p-substrate 802. The input node of the ESD protection device is connected to a P++ diffusion 814 inside n-well 808 and to N++ diffusion 818 inside n-well 806.
Between the various diffusions and wells are formed a plurality of shallow trench isolation (STI) structures 810. Shallow trench isolation structures 810 are trenches formed in the substrate 802 and filled with a dielectric such as silicon dioxide (SiO.sub.2) The STI 810 structures serve to isolate the diffusion regions and to define the N+ and P+ implants. The use STIs for isolation is becoming more common in CMOS technologies because of increased scaling to smaller dimensional spacing.
Again, the ESD device 800 is generally referred to as a dual diode device. In particular, the P++ diffusion 814 and the N-well 808 comprise a first diode, with the P++ diffusion 814 being the anode and the N-well 808 being the cathode. Likewise, the N++ diffusion 818 and the N-well 806 combine to form the cathode of the second diode with the P-type substrate 802 being the anode. Thus, the ESD device comprises two stacked diodes, with one attached to ground (through the substrate) and the other attached to Vdd, and with input node connected to the node between them. By connected the input node to other devices (i.e., input buffers), the input node is able to absorb electrostatic discharges before the device it is protecting is damaged.
The robustness of an ESD protection device is determined by the amount of discharge that can be absorbed by the ESD protection device without the ESD protection device failing. The techniques used to measure the robustness of an ESD protection device typically use a human body model (HBM) ESD simulator. A 100 pF capacitor is charged to a high voltage, a switch is closed, discharging the capacitor through a 1500 ohm resistor and into the ESD protection device. This process is generally repeated with increasing voltages until the ESD device fails at different ESD polarities.
As an example of ESD device 800 operation, assume an ESD pulse positive with respect to Vdd strikes the input node. This forward biases the P++ diffusion 814/n-well 808 junction (diode 1) and current flows laterally from the P++ diffusion 814 to both N++ diffusion 812 and N++ diffusion 816. The larger the ESD pulse, the larger the current.
The ESD protection device also provides protection for negative ESD pulses. For example, with Vdd attached to ground an ESD pulse that is negative with respect to ground causes current to flow from Vdd to the N-well diode. The negative pulse forward biases the N-well 806/substrate 802 diode, causing current to flow from the Vdd power supply to the input node. In particular, current flows from N+ diffusions 820 and 816 through their relative N-wells and into N-well 806 and N++ diffusion 818. These laterally flowing currents flow through NPN structures, with N-wells 804 and 808 acting as the emitter, the P-substrate 802 acting as the base, and the N-well 806 acting as the collector or a forward-biased parasitic lateral bipolar NPN transistor.
In all these cases, the current flowing under the STI structures 810 causes the regions directly under the STI structures 810 to significantly heat up by Joule heating. Initially, the peak occurs at the diode edges slightly above ambient due to current crowding at the N++ diffusion - STI corner. As the ESD current increases, the peak-heating center migrates toward the P++ diffusion along the SI-silicon interface and increases in temperature. This increase in temperature happens very quickly, within 17 to 25 nanoseconds of the peak ESD impulse current. During this time, little thermal diffusion has taken place and the temperature of the surrounding regions, and in particular, the area around P++ diffusion 814, is much lower than STI-silicon interface region.
This temperature gradient, if high enough, can lead to junction dopant migration and diodic failure. Thus, the temperature gradient caused by the Joule heating limits the robustness of prior art ESD protection devices.
Furthermore, in cases where the ESD current is high enough, the temperature under the STI can rise to the "intrinsic temperature" of silicon. The intrinsic temperature is the temperature at which intrinsic carrier concentration exceeds the doping concentration. This makes the region quasi-intrinsic and the generation rate of carriers increases, which in turn creates more heat and so on. The generation rate of carriers increases as the intrinsic carrier concentration increases with respect to the intrinsic recombination time. This process, called thermal runaway, continues until the ESD device fails.
For more information on ESD failures see J. M. Never and S. H. Voldman, Failure analysis of shallow trench isolated BSD structures, Journal of Electrostatics, Volume 38, pg. 93-112, (1996).
Prior art ESD devices have kept the width of the STI structures 810 relatively wide to help prevent thermal runaway from occurring. Unfortunately, this solution is not acceptable as the required device densities continue to increase. Therefore, what is needed is a method and structure for limiting the possibility of thermal runaway while allowing for increased device scaling and without requiring excessive mask layers and processing steps.